000 00437nam a2200169Ia 4500
001 aQ10723
008 220803s9999 xx 000 0 und d
020 _a9788177589184
100 _a Palnitkar, Samir
245 0 _aVerilog HDL A Guide to Digital Design and Synthesis IEEE 13-2001 Compliant
250 _a2nd
260 _c2013
300 _a490
600 _aElectronic Engineering
650 _aTechnology
942 _bBooks
_cBK
999 _c12454
_d12454